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Fundamental Technologies

Galileo Spacecraft Pages

Appendix A. EDR File Structure

Table of Contents

1. EPD Housekeeping Decom (below; please scroll down)
2. Spacecraft Clock (below; please scroll down)
3. EPD Subsystem Telemetry
4. EPD Telemetry Packet Definitions

1. EPD Housekeeping Decom

Source: GLL-SRD 90-07-10, Rev. C, pp. 4.7-17 - 4.7-18 (June 1984)

RIM	MOD 91	LRS Bits	No. of Bits	Channel No.	Function
Any	41	2129-2136	8	S-1687	EP MISC S1
"	47	2129-2136	8	S-1688	EP MISC S2
"	59	2129-2136	8	S-1689	EP MISC S3
"	03	2129-2133	5	S-1690	EPD SCAN 1
"	03	2134-2136	3	S-1691	EP MTR POS - 0,1,2,3,4,5,6,7
"	00	2161-2168	8	S-1692	EP CMDS EX
"	00	2177-2184	8	S-1693	EP CM CODE
"	00	2186	1	S-1694	EP PWR MON - NORMAL, INTER
"	02	2129-2136	8	S-1695	EP MOTOR T
"	04	2129-2136	8	S-1696	EPD SCAN 2
"	10	2129-2136	8	S-1697	EP LEMMS T
"	16	2129-2136	8	S-1698	EP CMS T
"	22	2129-2136	8	S-1699	EP ELECT T
"	28	2129-2136	8	S-1700	EPD INPUT I
"	34	2129-2136	8	S-1701	EP +60V
"	40	2129-2136	8	S-1702	LOG AMP T
"	46	2129-2136	8	S-1703	EP -15V
"	52	2129-2136	8	S-1704	EP +10V
"	58	2129-2136	8	S-1705	EPD +6V
"	64	2129-2136	8	S-1706	EPD +3V
"	70	2129-2136	8	S-1707	EP -3V
"	76	2129-2136	8	S-1708	EP -6V
"	82	2129-2136	8	S-1709	EP -10V
"	00	2187	1	S-1710	EP BUS PAR - NORMAL, ERROR
"	05	2129-2136	8	S-1711	EPD SCAN 3
"	09	2131-2136	6	S-1712	EPD SCAN 4
"	23	2129-2136	8	S-1713	EPD MEM CS
"	35	2129-2136	8	S-1714	EPD LEMMS D

2. Spacecraft Clock (SCLK)

Each GLL telemetry frame shall contain a S/C time field. The SCLK shall have the characteristic that it can be directly used to determine time, identify all measurements, and to correlate events to within the time resolution of the S/C clock.

The SCLK shall mark the first bit of the frame synchronization code time and shall represent the time interval in which the CDS collected the instrument data contained within the frame. The SCLK is shown in Figure 5 and is described below.

Figure 5. Spacecraft Clock (SCLK)

Real-Time Image Count (RIM). This field is a 24 bit counter which shall be incremented each 60 2/3 s (corresponding to a real-time image cycle). This clock shall keep unambiguous account of time for 32 years. The starting value of the counter shall be initialized at launch and shall not be reset after launch except from the ground after an interruption of power to the CDS memories. The maximum value of the SCLK shall not roll over until attaining the value 16777215.

Mod 91 Count (MOD91). The MOD91 counter is an 8 bit counter which shall be incremented once every 2/3 s. This field shall range in value from 0 through 90, with 0 corresponding to the start of the real-time solid state imaging cycle. This field shall increment by one every LRS frame.

Telemetry mode changes shall occur synchronously with (1) the rollover of the MOD91 count from 90 to 0 and (2) incrementing the RIM by 1.

Mod 10 Count (MOD10). The MOD10 counter is an 8 bit counter which shall be incremented once each 66 2/3 msec. This field shall range from 0 through 9, with the change to zero synchronous to the incrementing of the MOD91 count. This field shall increment by 1 for each frame transmitted or recorded at a telemetry rate greater than 7.68 kb/s. The MOD10 count is synonymous with the Real-Time Interrupt (RTI) in the CDS.

Mod 8 Count (MOD8). The MOD8 counter is an 8 bit counter which shall be incremented once each 8 1/3 ms. The field shall range from 0 through 7. With the change to 0 synchronous to the incrementing of the MOD10 count.

This field shall normally be zero in any frame being created at telemetry rates less than or equaling 115.2 kb/s. For those frames being routed to the DMS at rates exceeding 115.2 kb/s, the counter shall increment by one for each frame placed onto the DMS.

Next: 3. EPD Subsystem Telemetry

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Updated 10/19/04, T. Hunt-Ward
tizby@ftecs.com